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Last modified by Admin on 2025/03/18 12:51
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2 2  
3 3  Overall and mounting dimensions of the BMS Main 2.1 are shown in Figure 29.
4 4  
5 -[[Dimensions of the BMS Main 2.1>>image:1732198397369-222.png||data-xwiki-image-style-alignment="center" height="393" width="556"]]
5 +[[image:1732198397369-222.png||data-xwiki-image-style-alignment="center" height="393" width="556"]]
6 6  
7 7  |**Parameter**|**Value**
8 8  |(((
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24 24  
25 25  The BMS Main 2.1 headers are shown in figure below.
26 26  
27 -[[The BMS Main 2.1 headers>>image:1731516393377-928.jpeg||alt="1731517946345-632.png" data-xwiki-image-style-alignment="center" height="417" width="451"]]
27 +[[image:1731516393377-928.jpeg||alt="1731517946345-632.png" data-xwiki-image-style-alignment="center" height="417" width="451"]]
28 28  
29 29  (% class="wikigeneratedid" %)
30 30  Following chapters describes the BMS Main 2.1 headers pinout.
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40 40  
41 41  === 2.3.2 P15 – header for BMS Logic ===
42 42  
43 -[[image:1732198849079-697.png||height="77" width="71"]]
43 +[[image:1732198890482-787.png||height="77" width="71"]]
44 44  
45 +
45 45  (% style="width:524px" %)
46 46  |(% style="width:69px" %)**Pin**|(% style="width:97px" %)**Name**|(% style="width:355px" %)**Description**
47 47  |(% style="width:69px" %)**1**|(% style="width:97px" %)**RS485_A**|(% style="width:355px" %)RS-485 line A for communication with BMS Logic